Copyback memory system and cache memory controller which permits

Details Copyback memory system and cache memory controller which permits Copyback memory system and cache memory controller which permits

1992-01-17

1995-01-10

Atkinson, Charles E.

Boots, shoes, and leggings

36424341, 364DIG1, 395425, G11C 2900, G06F 1100

Patent

active

053815440

ABSTRACT:
A cache memory system for controlling a cache memory. The cache memory system is connected to a central processing unit and a main memory and the cache memory system is controlled to operate in a copyback operation mode. The cache memory system includes the cache memory which operates as cache memory to the central processing unit and a control circuit, responsive to detection of an error in the cache memory, for suspending an updating operation of an entry in the cache memory in which the error was detected, controlling access to valid entries in the cache memory, and causing the cache memory to operate as cache memory only when access from the central processing unit hits the valid entries of the cache memory.

REFERENCES:
patent: 5274799 (1993-12-01), Brant et al.
Computer, "A Survey of Cache Coherence Schemes for Multiprocessors", by Per Stenstrom, Jun. 1990, IEEE.
Computer, "A Case for Direct-Mapped Cache", Mark D. Hill, Dec. 1988, IEEE.

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