DMA controller including a FIFO register and a residual register

Details DMA controller including a FIFO register and a residual register DMA controller including a FIFO register and a residual register

1991-10-15

1995-01-10

Gossage, Glenn

Boots, shoes, and leggings

395575, 364DIG1, G06F 1300, G06F 1116

Patent

active

053815386

ABSTRACT:
A direct memory access (DMA) controller for exchanging data information between a system memory and an input/output (I/O) device in an initial data exchange mode and an alternate data exchange mode includes a register for exchanging the data information during both modes and a residual data register for storing residual data information in the register upon commencement of the alternate data exchange mode and for providing the residual data information when the initial data exchange mode is restarted.

REFERENCES:
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patent: 4996687 (1991-02-01), Hess et al.
patent: 5089958 (1992-02-01), Horton et al.
patent: 5159671 (1992-10-01), Iwami
patent: 5175825 (1992-12-01), Starr
Patent Abstracts of Japan--vol. 13, No. 191 (P-867) May 9, 1989 (JP 01-015845 (Hitachi Ltd.) Jan. 19, 1989).
IBM Technical Disclosure Bulletin, vol. 30, #1, Jun. 1987; pp. 337-339, "Direct Memory Access in a Multi-Tasking Environment".

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