Method and apparatus for separate mark and wait instructions for

Details Method and apparatus for separate mark and wait instructions for Method and apparatus for separate mark and wait instructions for

1994-05-25

1995-01-10

Eng, David Y.

Boots, shoes, and leggings

3642629, 364263, 3649467, 364973, G06F 1200, G06F 1300, G06F 1516

Patent

active

053815360

ABSTRACT:
The present invention provides a method and apparatus for handling memory hazards in processors having multiple memory ports wherein the operation of marking of the memory requests that may be related to a memory hazard is separated from the operation of waiting for the memory hazard to clear. The separation of the operation of marking of memory hazards from the operation of waiting for memory hazards to clear allows a compiler to schedule other instructions, as well as other memory operations not directed to the memory location involved in the memory hazard sequence, during the time between the operations of marking and waiting for the memory hazard to clear. The waiting period ends once it is clear that the marked memory requests will execute in the order in which they were issued.

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