Two layer neural network comprised of neurons with improved inpu

Details Two layer neural network comprised of neurons with improved inpu Two layer neural network comprised of neurons with improved inpu

1992-11-05

1995-01-10

Westin, Edward P.

395 27, G06F 700, H03K 190944

Patent

active

053815157

ABSTRACT:
A two-layer network according to the present invention is comprised of a first-layer array of electrically-adaptable synaptic elements, inter-layer connection circuitry comprised of electrically adaptable elements, and a second-layer array of electrically-adaptable synaptic elements. Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor in each electrically adaptable element, usually comprising the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. Each synaptic element in the synaptic array comprises an adaptable CMOS inverter or other amplifier circuit. The inputs to all first-layer synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The outputs of all first layer synaptic elements in a column are connected to a common sense amplifier on a sense line. The outputs of the sense amplifiers are connected to the inputs of the synaptic elements of the second layer of the array. The outputs of all synaptic elements in a given row in the second layer of the array are connected to a common row output line. In order to adapt the synaptic elements in the array, the voltages to which the synaptic elements in a given column of the first layer of the array is to be adapted are placed onto the input voltage lines, and the synaptic elements in column n are then simultaneously adapted by assertion of an adapt signal on the adapt line for the column. The voltages to which the synaptic elements of the second layer of the array are to be adapted are placed on the row outputs lines.

REFERENCES:
patent: 4962342 (1990-10-01), Mead et al.
patent: 5053638 (1991-11-01), Furutani et al.
patent: 5059920 (1991-10-01), Anderson et al.
patent: 5083044 (1992-01-01), Mead et al.
patent: 5220641 (1993-06-01), Shima et al.

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