Patent
1987-03-26
1989-07-04
James, Andrew J.
357 41, 357 45, 357 236, H01L 2978, H01L 2954, H01L 2348, H01L 2710
Patent
active
048455440
ABSTRACT:
A semiconductor integrated circuit device having first and second field-effect transistors, wherein the gate electrode of the first field-effect transistor is defined by a first-level conductor layer, while a wiring which is connected to the source or drain region of the first field-effect transistor is defined by a second-level conductor layer, and the gate electrode of the second field-effect transistor is defined by a combination of the first- and second-level conductor layers which are stacked one upon the other. Further, the respective gate electrodes of the first and second field-effect transistors are formed through respective gate insulator films which are formed on the principal surface of a semiconductor substrate in the same manufacturing step. By virtue of the above-described means, it is possible to reduce the area required for connection between the source or drain region of the first field-effect transistor and the wiring and to thereby increase the scale of integration of the device. In addition, it is possible to lower the resistance of the gate electrode of the second field-effect transistor and to thereby increase the operating speed of the device. Since the first and second field-effect transistors can be formed on a semiconductor substrate having no damage generated thereto, it is possible to increase the dielectric strength of the gate insulator film and to thereby improve the electrical reliability of the device.
REFERENCES:
patent: 4451841 (1984-05-01), Hori et al.
patent: 4612565 (1986-09-01), Shimizu et al.
patent: 4673969 (1987-06-01), Ariizumi et al.
patent: 4695864 (1987-09-01), Kawamoto
Nikkei Electronics, 5/25/81, pp. 130-144, Japan.
Hitachi , Ltd.
Jackson, Jr. Jerome
James Andrew J.
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