Timing interpolator in digital demodulator

Details Timing interpolator in digital demodulator Timing interpolator in digital demodulator

1997-08-22

1999-08-03

Pham, Chi H.

Pulse or digital communications

Equalizers

Automatic

375232, 375350, 364723, 364724011, 36472419, H03H 730

Patent

active

059334525

ABSTRACT:
A timing interpolator for re-controlling a symbol timing in a digital demodulator for converting a received analog signal to a digital signal is disclosed. The timing interpolator comprises an address generator for inputting M number of fractional intervals between 0 to 1 at each clock, and generating addresses from the fractional intervals; a memory for storing sine function values corresponding to the M number of fractional intervals, and outputting sine function values corresponding to the addresses from the address generator; a tap-coefficient calculator for receiving the filter index, the fractional intervals, and the sine function values, to calculate a tap-coefficient; and a digital filter having L+1 number of taps to filter an input signal by using the calculated tap-coefficient obtained from the tap-coefficient generator, and outputting the filtered signal. By using this structure, the timing interpolator stores M number of sine function values in the memory according to the variation of the filter index, the fractional interval, and the fractional interval instead of (L+1).times.M number of tap-coefficients, such that the interpolator's memory decreases by as much as 1/(L+1) by using the stored sine function values to directly calculate the tap-coefficients.

REFERENCES:
patent: 5159338 (1992-10-01), Takashasji
patent: 5398029 (1995-03-01), Tomaya et al.
patent: 5481568 (1996-01-01), Yada
patent: 5512895 (1996-04-01), Madden et al.

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