Error correction/detection circuit and semiconductor memory devi

Details Error correction/detection circuit and semiconductor memory devi Error correction/detection circuit and semiconductor memory devi

1996-03-06

1999-08-03

Baker, Stephen M.

Excavating

365200, 371 4017, 371 4018, G11C 2900

Patent

active

059334363

ABSTRACT:
An error correction/detection circuit including a syndrome generating circuit for generating a syndrome from information data and check data input in a first cycle; and an error position/size calculating circuit for calculating a position and a size of an error from said syndrome; and an error correction circuit for correcting an error for at least information data input in a second cycle on a basis of the position and the size of the error obtained in said error position/size calculating circuit and for outputting at least error-corrected information data.

REFERENCES:
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patent: 5313464 (1994-05-01), Reiff
patent: 5438577 (1995-08-01), Nakase et al.
patent: 5604703 (1997-02-01), Nagashima
Kiyohiro Furutani, et al. A Built-in Hamming Code ECC Circuit for Dram's, IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 50-55.
Toshio Yamada, et al. "A 4-MBIT DRAM with 16-Bit Concurrent ECC", IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988, pp. 20-25.
W.W. Peterson, et al. Error Correcting Codes, 2nd Edition, MIT Press, 1972, pp. 230-243.

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