Memory system having internal state monitoring circuit

Details Memory system having internal state monitoring circuit Memory system having internal state monitoring circuit

1997-01-28

1999-08-03

Tu, Trinh L.

Excavating

365201, G11C 2900, G11C 700

Patent

active

059334347

ABSTRACT:
A memory system having a test mode which can be used to access signals internally generated by the system during its operation. The signals accessible in the test mode are not available to a standard user of the system, but can be used by a memory chip designer to determine the cause of a device failure. The memory system includes a test signal switch which is used to route one of a multitude of internal signals to an input/output (I/O) pad where the information can be accessed by a chip designer. In order to access the internal signals, the memory system is first placed into a test mode, which acts to shut off the data paths used for reading the output of the sense amplifier included as part of the data read path or for reading the contents of the status register. A signal specifying a particular test signal of interest is then input. Decode logic is used to verify the coded input signal and control the multiplexer to route a specified internal signal through the switch to the I/O pad. By operating the memory system and monitoring the selected signal or data, a chip designer can isolate the cause of a device failure and investigate solutions to the problem without the need for micro-probing of the device.

REFERENCES:
patent: 4504784 (1985-03-01), Goel et al.
patent: 4550289 (1985-10-01), Kabashima et al.
patent: 4839865 (1989-06-01), Sato et al.
patent: 4970454 (1990-11-01), Stambaugh et al.
patent: 5030904 (1991-07-01), Tanksalvala et al.
patent: 5107208 (1992-04-01), Lee
patent: 5157629 (1992-10-01), Sato et al.
patent: 5177745 (1993-01-01), Rozman
patent: 5196787 (1993-03-01), Ovens et al.
patent: 5212442 (1993-05-01), O'Toole et al.
patent: 5233610 (1993-08-01), Nakayama et al.
patent: 5253255 (1993-10-01), Carbine
patent: 5459733 (1995-10-01), Alapat
patent: 5463585 (1995-10-01), Sanada
patent: 5498972 (1996-03-01), Haulin
patent: 5508631 (1996-04-01), Manku et al.
patent: 5581176 (1996-12-01), Lee
patent: 5619461 (1997-04-01), Roohparvar
patent: 5627478 (1997-05-01), Habersetzer et al.
patent: 5627838 (1997-05-01), Lin et al.
patent: 5642057 (1997-06-01), Oke et al.
patent: 5648730 (1997-07-01), Bhuva et al.
patent: 5657328 (1997-08-01), Swoboda

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