Method of adding two binary numbers and binary adder used therei

Details Method of adding two binary numbers and binary adder used therei Method of adding two binary numbers and binary adder used therei

1997-02-10

1999-08-03

Mai, Tan V.

Boots, shoes, and leggings

364749, G06F 750, G06F 738

Patent

active

059333626

ABSTRACT:
An adder has a carry signal generation block for producing carry generation signal bits representative of carry bits resulted from augend signal bits and addend signal bits and carry propagation signal bits representative of carry bits resulted from the augend signal bits, the addend signal bits and the carry bits supplied from lower-digits, a carry propagation block responsive to control signal bits for dividing the adder into partial adders and having propagation stages for producing carry signal bits from the carry generation signal bits, the carry propagation signal bits and the control signal bits, and a sum generation block for producing sum signal bits from the carry propagation signal bits, the control signal bits and the carry signal bits, and is divisible into an arbitrary number of partial adders without increase the stages of a critical path.

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Kohn et al., "The Visual Instruction Set (VIS) in UltraSPARC.TM.", IEEE, pp. 462-463 and 466-467, 1995.

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