Data processor having an execution unit controlled by an instruc

Details Data processor having an execution unit controlled by an instruc Data processor having an execution unit controlled by an instruc

1994-07-01

1995-02-28

Bowler, Alyssa H.

Boots, shoes, and leggings

395375, 3642318, 364DIG1, G06F 930

Patent

active

053945581

ABSTRACT:
A data processor in which, when two primitive instructions are decoded by instruction decoders, a microprogram ROM is not used under the control of a selector, and the two primitive instructions are executed in parallel by instruction execution units in accordance with the decoded outputs of the instruction decoders. When a high performance instruction is decoded by one of the instruction decoders, at a first step processing, one of the instruction execution units selects the output of the one instruction decoder to execute the instruction. At a second step processing, the one instruction execution unit selects a microinstruction of the microprogram ROM and executes the instruction. It is therefore unnecessary to use the microprogram ROM for the execution of a primitive instruction and a high performance instruction at the first step processing, thereby reducing the capacity, area and power consumption of the microprogram ROM.

REFERENCES:
patent: 4519033 (1985-05-01), Vaughn et al.
patent: 4574344 (1986-03-01), Harris et al.
patent: 4658355 (1987-04-01), Hatakeyama et al.
patent: 4812972 (1989-03-01), Chastain et al.
patent: 5202967 (1993-04-01), Matsuzaki et al.
patent: 5247624 (1993-09-01), Koumoto et al.
Byte, Nov. 1989, vol. 14, No. 12, pp. 323-329.

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