RAM buffer controller for providing simulated first-in-first-out

Details RAM buffer controller for providing simulated first-in-first-out RAM buffer controller for providing simulated first-in-first-out

1990-08-13

1992-07-21

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 364239, 36423951, 364252, 3642563, G06F 1200, G06F 1210

Patent

active

051330628

ABSTRACT:
A RAM buffer is provided for managing the address inut lines of a RAM buffer to simulate the operation of two FIFO's therein. In addition, an apparatus is provided for allowing random access by a node processor in a local area network node using the RAM buffer controller to manage transmit and receive FIFO's to have random access to any address in the address space of the buffer without restriction to FIFO boundaries. Also disclosed is an apparatus for transmitting packets from said buffer organized into one or two linked lists. Further, an apparatus is provided for allowing independent initialization of any of the pointers in the RAM buffer controller which are not currently selected, and for allowing software requests for read or write access by the node processor. Further, an apparatus and a method are provided for recording status and length information at the end of a packet instead of in front thereof and for allowing any incoming packet to be flushed without saving status information or to be flushed while saving its status information.

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