Method of fabricating a semiconductor device

Details Method of fabricating a semiconductor device Method of fabricating a semiconductor device

1994-02-02

1995-01-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 6, 437203, 437911, 148DIG126, H01L 21265

Patent

active

053806700

ABSTRACT:
An N.sup.+ buffer layer (2) and an N.sup.- layer (3) are provided on a P.sup.+ silicon substrate (1) in this order. On an upper portion of the N.sup.- layer (3), a P.sup.- layer (4b) is selectively formed, and on the P.sup.- layer (4b), a P.sup.+ layer (4a) is provided. On part of a top surface of the P.sup.+ layer (4a), a plurality of N.sup.+ layers (5a) are provided, and a trench (13) is formed extending through each of the N.sup.+ layers (5a) and P.sup.+ layer (4a) downwards to the P.sup.- layer (4b). In the P.sup.- layer (4b), an N.sup.+ floating layer (5b) is provided covering the bottom face of each trench (13). In the inner hollow of the trench (13), a gate electrode (8a) is provided through a gate oxidation film (7a), while an emitter electrode (9a) is provided extending between the top surfaces of the adjacent N.sup.+ layers (5a) with the surface of the P.sup.+ layer (4a) interposed so as to electrically short circuit them. A collector electrode (10) is provided on a lower major surface of the P.sup.+ substrate (1). When a higher potential than that of the emitter electrode (9a) is applied to the gate electrode (8a) with forward bias being applied between the electrodes (9a) and (10) so that the collector electrode (10) may be higher in potential than the emitter electrode (9a), the channel region (6a) turns to the N-type, and electrons move from the N.sup.+ layers (5a) through 26e channels (6a) to the N.sup.+ floating layers (5b).

REFERENCES:
patent: 4799095 (1989-01-01), Baliga
patent: 4872044 (1989-10-01), Nishizawa et al.
patent: 4898835 (1990-02-01), Cawlfield
patent: 5086007 (1992-02-01), Ueno
patent: 5173435 (1992-12-01), Harada
patent: 5202750 (1993-04-01), Gough

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