Method for fabricating double implanted LDD transistor self-alig

Details Method for fabricating double implanted LDD transistor self-alig Method for fabricating double implanted LDD transistor self-alig

1989-11-24

1990-10-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437186, 437191, 437192, 437228, 437229, 437233, 156643, H01L 21265

Patent

active

049635042

ABSTRACT:
An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment member and a heavily doped junction is aligned with the outboard alignment members.

REFERENCES:
patent: 4818715 (1989-04-01), Chao
patent: 4837180 (1989-06-01), Chao
Huang et al., "A Novel Submicron LDD Transistor with Inverse-T Gate Structure", IEDM, 12/1986, pp. 742-745.
Wolf et al., Silicon Processing for the VLSI Era, vol. 1, Process Technology, Lattice Press, 1986, pp. 397-399.

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