Method of making semiconductor having improved interlevel conduc

Details Method of making semiconductor having improved interlevel conduc Method of making semiconductor having improved interlevel conduc

1993-01-21

1995-02-28

Thomas, Tom

Fishing, trapping, and vermin destroying

H01L 2170

Patent

active

053936906

ABSTRACT:
A semiconductor device and method of manufacture employs an improved insulating layer to laterally separate conductive layers or regions. A relatively thick insulating layer is anisotropically patterned to form an electrode having a thick insulating layer on its side walls. Subsequently defined conductive regions are separated from the electrode by a distance determined by the thickness of the insulating layer. In devices requiring multiple level polycrystalline silicon electrodes, shorts between electrodes are reduced; in MOS devices, operating parameters are improved due to decreased overlap of the gate electrode over the source or drain region, decreased contamination of the gate electrode during manufacture, and more uniform gate oxide definition along the active channel between the source and drain.

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patent: 4087832 (1978-05-01), Jambotkar
patent: 4227202 (1980-10-01), Tasch, Jr. et al.
patent: 4228445 (1980-10-01), Tasch, Jr. et al.

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