Method of manufacturing a stacked capacitor DRAM

Details Method of manufacturing a stacked capacitor DRAM Method of manufacturing a stacked capacitor DRAM

1993-11-24

1995-02-28

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

053936884

ABSTRACT:
A storage node of a stacked capacitor in a DRAM comprises a first part connected to a source/drain region and a second part protruding upward from a substrate in a vertical wall shape. The second part includes a concave part in the inner part which is removed by etching. Steps are formed on the inner and outer peripheral surfaces of the vertical wall part. The steps are formed by a self-alignment method using a sidewall insulating layer formed by anisotropic etching. Capacitance of the capacitor is increased by forming steps on the surface of the storage node.

REFERENCES:
patent: 5002896 (1991-03-01), Naruke
patent: 5134086 (1992-07-01), Ahn

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