Optimization of BV and RDS-on by graded doping in LDD and other

Details Optimization of BV and RDS-on by graded doping in LDD and other Optimization of BV and RDS-on by graded doping in LDD and other

1990-03-23

1992-07-21

Mintel, William

357 238, 357 90, H01L 2910

Patent

active

051327538

ABSTRACT:
Transistor structure using a lightly doped drain (LDD) technique are disclosed. The present invention provides a reduced on-resistance in the LDD region, while retaining substantially all the high breakdown voltage advantage of the LDD technique. The advantage of the present invention is achieved by applying a non-uniform impurity design in the LDD region, increasing gradually from the gate-edge towards the contact.

REFERENCES:
patent: 4933730 (1990-06-01), Shirato
Bassous, E. et al., "Self-Aligned Polysilicon Gate MOSFET's with Tailored Source and Drain Profiles", IBM Technical Disclosure Bulletin, vol. 22 No. 11, Apr. 1980, pp. 5146-5147.

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