Television – Bandwidth reduction system – Data rate reduction
Patent
1996-05-03
1998-10-06
Chin, Tommy P.
Television
Bandwidth reduction system
Data rate reduction
348414, H04N 712, H04N 1102, H04N 1104
Patent
active
058185321
ABSTRACT:
Disclosed is a reusable hardware layout ("core") for performing some, but not all, MPEG-2 video decoding functions. The information content of the core may be stored on a machine readable media and includes a series of hardware layouts specifying the locations and features of various circuit elements comprising the video core architecture. The disclosed video decoder core design specifies that at least the following MPEG-2 functions are performed by the hardware: inverse scan, inverse quantization, inverse discrete cosine transform, half pel compensation, and merge. Other MPEG-2 functions such as motion vector decoding, variable length decoding, and run level decoding are not performed by hardware video cores fabricated in accordance with video core design. To implement the specified video core MPEG-2 functions, the video core employs, as architecturally distinct logic blocks, an inverse quantization unit, an inverse discrete cosine transform unit, a half pel compensation unit, a merge and store unit, and registers storing control information used by the other units.
REFERENCES:
patent: 5126726 (1992-06-01), Howard et al.
patent: 5394473 (1995-02-01), Davidson
patent: 5448310 (1995-09-01), Kopet et al.
patent: 5473631 (1995-12-01), Moses
patent: 5506832 (1996-04-01), Arshi et al.
patent: 5515107 (1996-05-01), Chiang et al.
patent: 5576765 (1996-11-01), Cheney et al.
patent: 5576958 (1996-11-01), Kawakatsu et al.
patent: 5594789 (1997-01-01), Seazholtz et al.
patent: 5598352 (1997-01-01), Rosenau et al.
patent: 5623311 (1997-04-01), Phillips et al.
patent: 5635985 (1997-06-01), Boyce et al.
patent: 5638128 (1997-06-01), Hoogenboom et al.
Martin Boliek, "Real-Time Discrete Cosine Transform Chip Using Generalized Chen Transform Technology," pp. 428-431, Ricoh California Research Center, Menlo Park, CA.
Unknown, "Digital Audio Compression (AC-3)," T3 review copy of draft ATSC audio standard, Aug. 12, 1994, Doc. T3/251.
Unknown, "Information Technology-Generic Coding of Moving Pictures and Associated Audio Information: Video," ISO/IEC 13818-2, Draft International Standard, Nov. 9, 1994.
Unknown, "Coding of Moving Pictures and Associated Audio," ISO/IEC 13818-3, International Standard, Nov. 11, 1994.
Dave Bursky, "Single Chip Performs Both Audio and Video Decoding," Electronic Design, Apr. 3, 1995.
Unknown, "Coding of Moving Pictures and Associated Audio for Digital Storage Media At Up To About 1.5 MBIT/s," 3-11171 rev. 1, (Part 3 Audio), May 30, 1995.
Jones, et al., "Futurebus Interface from Off-the-Shelf Parts", IEEE, pp. 38-41, Continue on pp. 84-93, Feb. 1991.
J. DeTar, "LSI Logic adds to telecom-specific core library", Electronic News, p. 25, Sep. 19, 1994.
F. Gardner, "LSI eases PCI bus development", Electronic News, p. 197, Aug. 1, 1994.
L. Gwennap, "LSI delivers MPEG decoder for digital TV", p. 20, Microprocessor Report, May 10, 1993.
C. Joly, et al., "ASIC integration relies on reusable cores", Electronic Engineering Times, p. 46, May 1, 1995.
Unknown, "Coding of Moving Pictures and Associated Audio-for Digital Storage Media at up to about 1.5 Mbit/s", Aug. 2, 1996, ISO, CD 11172-1 rev. 1.
Malladi Srinivasa R.
Mattela Venkat
Chin Tommy P.
Diep Nhon T.
LSI Logic Corporation
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