Process for fabricating double poly high density buried bit line

Details Process for fabricating double poly high density buried bit line Process for fabricating double poly high density buried bit line

1993-07-14

1995-02-28

Thomas, Tom

Fishing, trapping, and vermin destroying

437 45, 437 49, 437 50, 437225, H01L 2170

Patent

active

053932331

ABSTRACT:
In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.

REFERENCES:
patent: 5063170 (1991-11-01), Okuyama
patent: 5200355 (1993-04-01), Choi et al.
patent: 5264386 (1993-11-01), Yang
patent: 5278078 (1994-01-01), Kanebako et al.
Okada et al, "16 Mb ROM Design Using Bank Select Architecture," Integrated Circuits Group, Sharp Corp., 2613-1, Ichinomoto, Tenri, Nara 532 Japan.

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