Process for manufacturing EEPROM memory cells having a single le

Details Process for manufacturing EEPROM memory cells having a single le Process for manufacturing EEPROM memory cells having a single le

1990-08-30

1992-07-21

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437979, H01L 21336

Patent

active

051322390

ABSTRACT:
The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor, sensing transistor having a floating gate, control gate with a capacitive coupling to the floating gate and a tunnel area with thin oxide, comprises a first step involving the definition of active areas free of field oxide, a second step involving an ionic implantation at a coupling area between the control gate and the floating gate, a third step involving the creation of gate oxide at the active areas, a fourth step involving an additional ionic implantation at said coupling area between the control gate and the floating gate and at said tunnel area, a fifth step involving the removal of the gate oxide superimposed over said areas, a sixth step involving the differentiated growth of coupling oxide and tunnel oxide at said coupling areas and tunnel areas and a seventh step involving the deposition of a layer of polysilicon constituting the floating gate.

REFERENCES:
patent: 4019197 (1977-01-01), Lohstroh et al.
patent: 4049477 (1977-09-01), Ligon

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