Microprocessor having variable data width

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G06F 1300

Patent

active

047665386

ABSTRACT:
A microprocessor having variable data width comprising a bus cycle changeover circuit between a command execution unit and each of an address output logic, a data input/output logic, and a bus controller. The bus cycle changeover circuit receives an address, data, a memory access instruction and a data width instruction from the command execution unit and modifies timings of them according to an externally supplied data width selection signal and transmits modified address, data, memory access instruction and data width instruction signals to the address output logic, the data input/output logic and the bus controller. The bus cycle changeover circuit comprises a cycle control circuit which outputs a signal expressing a latter half access cycle and an upper/lower selection circuit which selects upper/lower parts of the data bus according to an output signal of the cycle control circuit.

REFERENCES:
patent: 4466055 (1984-08-01), Kinoshita et al.
patent: 4663729 (1987-05-01), Matick et al.
patent: 4667305 (1987-05-01), Dill et al.
Intel Microcomputer Components Handbook, Intel Corporation, 1980, pp. 3-412 through 416 and 3-334 through 337.

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