Patent
1986-12-29
1988-08-23
James, Andrew J.
357 41, 357 42, 357 45, H01L 2702
Patent
active
047664754
ABSTRACT:
A semiconductor integrated circuit device which includes input and output buffers having a high versatility of design is disclosed. Each buffer provided in correspondence with a bonding pad is made usable for either the input buffer or the output buffer in accordance with a wiring pattern to be formed therein. With this arrangement, it is possible to use the same circuit elements for both the input buffer and the output buffer. Thus, circuit elements to be exclusively used for inputting and outputting respectively need not be separately formed, and the area occupied by the buffers is reduced to that extent, to realize an increase in the number of pins or a reduction in the size of a chip. In addition, since one buffer can be set for either inputting or outputting, enhancement in the versatility of the design of the pins or the chip is achieved.
REFERENCES:
patent: 3712995 (1973-01-01), Steubel
patent: 3746946 (1973-07-01), Clark
patent: 4255672 (1981-03-01), Ohno et al.
patent: 4513307 (1985-04-01), Brown
Battista, "Multiple Function (I/O) Cell Layout," IBM Technical Disclosure Bulletin, vol. 22, No. 7, Dec. 1979, pp. 2772-2774.
Sasaki et al., "A CMOS/SOS Gate Array with a New Customization Technique of Cutting," IEEE Transactions on Electron Devices, vol. ED-29, No. 10, Oct. 1982, pp. 1535-1541.
Hitachi , Ltd.
James Andrew J.
Mintel William A.
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