Planarization process

Details Planarization process Planarization process

1987-11-18

1989-11-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437189, 437246, 437228, 437978, 437192, 148DIG51, 148DIG131, 148DIG81, 1566591, 156653, H01L 21283, H01L 21316

Patent

active

048792578

ABSTRACT:
A method for forming a multilayer integrated circuit is described wherein the resultant top surface thereof is substantially planar. The method involves first forming a layer of connecting metallization on integrated circuit components formed in a conventional manner. Then a first layer of dielectric is formed on the metallization layer. Next a second dielectric layer is formed on the first dielectric layer. Via areas are then formed by etching the first and second dielectric layers in order to expose selected areas of the first metallization layer, and filled with metal to form vias. A layer of photoresist is deposited on all surfaces. Lastly, the surface is etched using an etchant that etches dielectric, metal and photoresist at substantially the same rate such that said vias are exposed and a planar top surface produced.

REFERENCES:
patent: 4038110 (1977-07-01), Feng
patent: 4470874 (1984-09-01), Bartush et al.
patent: 4520041 (1985-05-01), Aoyama et al.
patent: 4541168 (1985-09-01), Galie et al.
patent: 4541169 (1985-09-01), Bartush
patent: 4666553 (1987-05-01), Blumenfeld et al.
patent: 4708767 (1987-11-01), Bril
patent: 4708770 (1987-11-01), Pasch

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