Method of manufacturing a DMOS

Details Method of manufacturing a DMOS Method of manufacturing a DMOS

1988-06-09

1989-11-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437150, 437151, 437203, 437228, 437984, 437947, 148DIG111, 148DIG126, 148DIG131, 148DIG103, H01L 21316

Patent

active

048792543

ABSTRACT:
A method for manufacturing a DMOS which comprises forming a first conductive type layer on a substrate, forming a gate oxide layer thereon, forming a gate electrode layer and a second insulating layer successively on the gate oxide layer, forming a second conductive type body region and a first conductive type source region having a narrower width by implanting impurities utilizing the second insulating layer as a mask, forming a side wall spacer of an insulating material on at least a side portion of the gate electrode, forming a conductive passage penetrating the source region and extending into the body region while utilizing the second insulating layer and the side wall spacer as mask, optionally implanting the exposed body region, further excessively etching the sidewall spacer, the masking layer overlying the gate, and the gate oxide prior to providing an electrode connecting the source and body regions.

REFERENCES:
patent: 4430792 (1984-02-01), Temple
patent: 4503598 (1985-03-01), Vora et al.
patent: 4567641 (1986-02-01), Baliga et al.
patent: 4598461 (1986-07-01), Love
IEEE Electron Device Letters, vol. EDL-8, No. 4, Apr. 1987, Huang et al., "A New LDD Transistor with Inverse-T Gate Structure", (pp. 151-153).
IEEE Transactions on Electron Devices, vol. ED-31, No. 4, Apr. 1984, Ueda et al., "A New Vertical Double Diffused MOSFET-The Self-Aligned Terraced-Gate MOSFET", (pp. 416-420).

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