Frequency multiplier using a voltage controlled delay circuit

Details Frequency multiplier using a voltage controlled delay circuit Frequency multiplier using a voltage controlled delay circuit

1997-03-05

1999-09-21

Le, Dinh T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327114, 327113, 327261, 327158, 327149, 327263, H03K 5159

Patent

active

059559020

ABSTRACT:
A voltage controlled delay circuit is comprised of a plurality of stages of delay cells and produces a 2N number of signals delayed behind a reference signal in units of time corresponding to 1/2N the delay time between the reference signal supplied to an input terminal of a first stage delay cell and a signal output from a final stage delay cell. A phase coincidence is achieved between the reference signal and the output signal from the final stage delay cell by a loop including a phase comparator, lowpass filter and voltage controlled delay circuit. An N multiplying logic circuit produces an N multiplied signal from the reference signal with only falls or rises of 2N delay signals.

REFERENCES:
patent: 5463337 (1995-10-01), Leonovich

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