Method of fabricating a vertical FET device with low gate to dra

Details Method of fabricating a vertical FET device with low gate to dra Method of fabricating a vertical FET device with low gate to dra

Filed on

1990-10-31

Date issued

1991-12-17

Examiner

Chaudhuri, Olik

Patent Class

Fishing, trapping, and vermin destroying

Other Related Categories

437 41, 437 44, 437186, 437233, 357 234, H01L 2128, H01L 21336

Type

Patent

Status

active

Patent number

050735195

Description

ABSTRACT:
This is a vertical MOSFET device with low gate to drain overlap capacitance. It can comprise a semiconductor substrate 22 of the first conductivity type, a source region 24,26 of a second conductivity type formed in the upper surface of the substrate 22; a vertical pillar with a channel region 28 of the first conductivity type, a lightly doped drain region 30 of the second conductivity type and a highly doped drain contact region 32 of the second conductivity type; a gate insulator 34, and a gate electrode 36 surrounding the vertical pillar not substantially extending into the highly doped drain contact region 30. This is also a method of forming a vertical MOSFET device on a single crystal semiconductor substrate, the device having a pillar on the substrate, with the pillar having a channel region in a lower portion and with the channel region having a top and a highly doped first source/drain region in an upper portion of the pillar, with the substrate having a highly doped second source/drain region and with a gate insulator on the substrate and on the pillar. The method comprises: isotropically forming a gate electrode material layer on the pillar and the substrate; anisotropically depositing a gate height determining insulator material on horizontal surfaces to at least the top of the channel region but not substantially overlapping the first highly doped source/drain region; and etching exposed gate electrode material to remove exposed gate electrode material above the gate height determining insulator material.

REFERENCES:
patent: 4338618 (1982-07-01), Nishizawa
patent: 4603468 (1986-08-01), Lam
patent: 4630088 (1986-12-01), Ogura et al.
patent: 4670768 (1987-06-01), Sunami
patent: 4902640 (1990-02-01), Sachitano et al.
patent: 4951102 (1990-08-01), Beitman et al.
patent: 4954854 (1990-09-01), Dhong et al.
patent: 4982258 (1991-01-01), Baliga
patent: 5001526 (1991-03-01), Gotou
International Electronics Device Meeting (IEDM) 1988, Takato et al., High Performance CMOS Surrounding Gate Transitor . . . , pp. 222-225.

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