Method for manufacturing a conductivity modulation MOS semicondu

Details Method for manufacturing a conductivity modulation MOS semicondu Method for manufacturing a conductivity modulation MOS semicondu

1989-03-29

1991-12-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 29, 437 81, 437 95, 148DIG26, H01L 21336

Patent

active

050735110

ABSTRACT:
The thin buffer layer, very often present in HIMOS devices, is achieved by ion implantation or predeposition of the dopant followed by subsequent diffusion.

REFERENCES:
patent: 4364073 (1982-12-01), Becke et al.
patent: 4696701 (1987-09-01), Sullivan
Di-Son Kuo, "Optimization of Epitaxial Layers for Power Bipolar-MOS Transistor" IEEE Elect. Devices Letters, Sep. 1986, pp. 510-512.
Toaliga et al., "The Insulated Gate Transistor: a New Three Terminal Mos-Controlled Bipolar Device" IEEE Trans. on Elec. Devices, Jun. 84, pp. 821-827.
Hefner et al., "Performance Trade-Off . . . ", I.E.E.E. Transactions on Power Electronics, PE-2 (1987) Jul., No. 3, pp. 194-207.
Russell et al., "HIgh-Power Conductivity-Modulated . . . ", 8179 IEEE Electron Device Letters, EDL-5 (1984) Nov., No. 11, pp. 437-439.

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