Static random access memory with address transition detector

Details Static random access memory with address transition detector Static random access memory with address transition detector

1989-03-28

1990-05-01

Fears, Terrell W.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365207, 36518908, 3652335, G11C 1300

Patent

active

049224611

ABSTRACT:
When an address transition detector detects a transition of an address signal, it produces an address transition detect signal. The signal drives a bit line initializing circuit which in turn initializes paired bit lines, and initializes the paired output lines of a sense amplifier. At the same time, a clock signal generator generates a clock signal for a predetermined period of time in accordance with the address transition detect signal. The clock signal is supplied to the sense amplifier and a data output circuit. The sense amplifier is active during a period that the clock signal from the clock signal generator is in an effective level. The output terminal of the data output circuit is placed in a high impedance state during the period that the clock signal is in an effective level. During the other periods than the effective level period, the data output circuit produces a signal corresponding to the data as is read out of a memory cell and outputted by the sense amplifier.

REFERENCES:
patent: 4592026 (1986-05-01), Matsukawa et al.
patent: 4592028 (1986-05-01), Konishi
patent: 4612631 (1986-09-01), Ochii
patent: 4701889 (1987-10-01), Ando

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