Method of reducing wearout in a non-volatile memory with double

Details Method of reducing wearout in a non-volatile memory with double Method of reducing wearout in a non-volatile memory with double

1988-04-29

1990-05-01

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365228, 365200, 36518905, 371 66, G11C 700, G11C 1140

Patent

active

049224565

ABSTRACT:
A method of preventing a power failure from corrupting data being written to a non-volatile memory. Before a write operation is performed, information is written to a double buffer to reconstruct the steps that will be performed during the write operation. A flag is set indicating that the information in the double buffer is accurate. The write operation is then performed and the flag is cleared. The double buffer is dynamically moved throughout the non-volatile memory to distribute the wearout of the non-volatile memory as evenly as possible.

REFERENCES:
patent: 4393500 (1983-07-01), Imazeki et al.
patent: 4442501 (1984-04-01), Eckert, Jr. et al.
patent: 4447887 (1984-05-01), Imazeki et al.
patent: 4493083 (1985-01-01), Kinoshita
patent: 4564922 (1986-01-01), Muller
patent: 4612632 (1986-09-01), Olson
patent: 4663770 (1987-05-01), Murray et al.

Affiliated with

Also associated with

Rating

Method of reducing wearout in a non-volatile memory with double does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of reducing wearout in a non-volatile memory with double , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing wearout in a non-volatile memory with double will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-834828