Boots – shoes – and leggings
Patent
1985-12-11
1990-05-01
Williams, Jr., Archie E.
Boots, shoes, and leggings
364955, 3642551, G06F 1210, G06F 1300
Patent
active
049224158
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computers and is particularly concerned with the performance and reliability of computer systems including a standard CPU, such as the Motorola MC 68000, INTEL iAPX 286, etc., and the memory accessed from such CPUs. The invention allows machine instructions of a standard CPU to be utilized in a much more efficient and reliable way than is otherwise possible.
There now follows a general description of the technical background to the invention followed by a detailed description of some specific embodiments of the invention with references to the accompanying drawings.
2. Background of the Invention
FIG. 1 shows a simplified block diagram of a computing system. This system is not the subject of the invention, but introduced in order to be able to explain the background to, and the salient points of, the invention. The main parts of the computing system in FIG. 1 are the Central Processing Unit (CPU) 10, the Memory (M) 40, and the Input/Output Interface (IO) 60 to the external world. The CPU contains a Control Logic function (CL) 12, which is not described in detail, and four registers; a Program Counter register (PC) 14, an Address Register (AR) 16, a Data Register (DR) 18 and an Instruction Register (IR) 20. The information stored in these registers can be read and written by CL 12. The memory (M) 40 contains N memory words (MW.sub.0, MW.sub.1, . . . MW.sub.N-1), and an Address Decoder (AD) 42, the input of which is connected to the Program Counter (PC) 14 and the Address Register (AR) 16 of the CPU 10. Each memory word contains a specific number of binary memory elements, each one of which may store either 0 to 1. All the memory words are connected to the Data Register (DR) 18 of the CPU 10, i.e. the contents of any memory word may be transferred to DR 18 and vice versa. The Control Logic (CL) 12 of the CPU has two control outlets, a Read Outlet (R) 22 and a Write Outlet (W) 24, which are connected to all the memory words in parallel. When CL 12 issue a Read command, the Address Decoder (AD) 42 selects the Memory Word, which corresponds to the contents of the Address Register (AR) 16 or the Program Counter (PC) 14, and the R Control Outlet 22 from CL 12 enables the transfer of information from the selected memory word into the Data Register (DR) 18 if the address is obtained from the Address Register (AR) 16, and into the Instruction Register (R) 20 if the address is obtained from the Program Counter (PC) 14. If a Write Command is issued, the W Control Outlet 24 from CL 12 enables the transfer of information from the Data Register (DR) 18 into the memory word addressed by the Address Register (AR) 16.
The information stored in the memory words can be used in two different ways, either as data or as control instructions.
When the information stored in a memory word is used as data, the separate binary memory elements are combined together to form a single value (V.sub.m) 70 according to the principle shown in FIG. 2a. This value can then be manipulated by the CL 12 in the desired manner, e.g. arithmetic operations, logic operations, etc. For a memory word MX.sub.x 72 containing m binary memory elements or bits, the total number of different data values represented by different combinations of the m bits, which can be stored in the memory word is 2.sup.m. These bit combinations may be used to represent values ranging from 0 to 2.sup.m -1 as illustrated by the example of the possible values for a 4-bit memory word in FIG. 2b. In special cases (e.g. binary coded decimal values) the value range may be further restricted. It is to be noted, that the manipulation of data values in CL 12 will give the correct result only as long as the result values do not exceed the number of bits, which can be manipulated and stored. In a system with 4-bit memory words and 4-bit control logic the addition 8+8 would give the result 0 instead of 16, because the representation of 16 in a four bit system would be 0. It is also to be noted that the inform
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Mohamed Ayni
Williams Jr. Archie E.
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