LSI layout design method capable of satisfying timing requiremen

Details LSI layout design method capable of satisfying timing requiremen LSI layout design method capable of satisfying timing requiremen

1997-06-26

1999-12-07

Teska, Kevin J.

3955001, 39550012, 39550003, 39550009, G06F 1750

Patent

active

059997168

ABSTRACT:
An LSI layout design technique is disclosed which has the ability to satisfy LSI timing constraints in a short processing time. A netlist descriptive of a target circuit that is designed is fed to a computer, and a flip-flop netlist representing information about connections among flip-flops relating to the timing constraints, is generated from the netlist. Such a flip-flop netlist is generated by clustering using a flip-flop as a seed. According to the generated flip-flop netlist, each flip-flop is placed and a flip-flop region to place therein a cell relating to a flip-flop is determined. A cell relating to a corresponding flip-flop is placed in a flip-flop region and the cell arrangement is improved throughout the placement region. Based on the improved cell arrangement, a layout is designed.

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Itoh et al "Ale: A Layout Generating and Editing System for Analog LSIs," IEEE, pp. 843-846, 1990.

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