High speed true/complement driver

Details High speed true/complement driver High speed true/complement driver

1977-06-16

1978-12-12

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 307251, 307279, 365206, 365230, 307DIG1, H03K 1760, H03K 1716, H03K 1940, G11C 800

Patent

active

041297938

ABSTRACT:
A high speed true/complement driver circuit is disclosed wherein the time interval between the address and memory select pulses are minimized by utilizing a high speed enhancement/depletion mode inverter pair followed by a clocked signal isolation stage. A pair of enhancement mode/depletion mode inverters connected in cascade configuration serves to generate the true and complement output signals which are isolated from noise at the input line by a symmetric pair of clocked FETs.

REFERENCES:
patent: 3575613 (1971-04-01), Ebertin
patent: 3700981 (1972-10-01), Masuhara et al.
patent: 3868657 (1975-02-01), Hoffman et al.
patent: 3922647 (1975-11-01), Broeker, Jr.
patent: 3938109 (1976-02-01), Gionis et al.
patent: 3946369 (1976-03-01), Pashley
patent: 3959781 (1976-05-01), Mehta et al.
patent: 3964030 (1976-06-01), Koo
patent: 4031415 (1977-06-01), Redwine et al.
Furman, "Address Buffer True/Complement Generator"; IBM Tech. Discl. Bull., vol. 18, No. 11, pp. 3597-3598; 4/1976.
Anderson, "Address Encoding Circuit"; IBM Tech. Discl. Bull.; vol. 17, No. 3 pp. 796-797; 8/1974.
Gladstein et al, "Low-Power Ratioless True-Complement Buffer"; IBM Tech. Discl. Bull.; vol. 18, No. 8, pp. 2591-2592;1/1976.

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