Circuit for the detection of address transitions

Details Circuit for the detection of address transitions Circuit for the detection of address transitions

1988-08-23

1990-05-01

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307481, 3072721, H03K 19017

Patent

active

049221221

ABSTRACT:
A circuit for the detection of address transistions in an integrated circuit comprises a logic signal input terminal, a D flip-flop for memorizing the state of the input signal, and a comparator having a first input terminal connected to the logic signal input terminal and a second input terminal connected to the output terminal of the memorizing means. The comparator gives a first logic level when its input terminals receive a same logic signal level and a second logic signal level when its input terminals receive different logic signal levels. This circuit enables the generation of an output pulse as soon as there is an input address transition, in such a way that the time delay of the output with respect to the address transition is kept to a minimum and the duration of the pulse is suitable for use in the integrated circuit which is sought to be activated.

REFERENCES:
patent: 4337525 (1982-09-01), Akatsuka
patent: 4446389 (1984-05-01), Williams et al.
patent: 4496861 (1985-01-01), Bazes
patent: 4518872 (1985-05-01), Backes
patent: 4598216 (1986-07-01), Lauffer et al.

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