Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-06-25
1999-12-07
Mai, Son
Static information storage and retrieval
Floating gate
Particular biasing
36518503, 257316, 257321, G11C 1604, H01L 29788
Patent
active
059994533
ABSTRACT:
A nonvolatile semiconductor memory includes a memory cell constituted by at least first and second floating gates, first and second control gates, and a source and a drain. The first floating gate is formed on a semiconductor substrate through a gate insulating film. The second floating gate is formed on a region without the first floating gate via the gate insulating film. The first control gate is formed on the first floating gate via an insulating film. The second control gate is formed on the second floating gate via the insulating film. The source and the drain are formed in the semiconductor substrate to sandwich the first and second floating gates.
REFERENCES:
patent: 5739568 (1998-04-01), Kojima
patent: 5753950 (1998-05-01), Kojima
patent: 5798548 (1998-08-01), Fujiwara
M. Ohkawa, et al., "TP 2.3: A 08mm.sup.2 3.3V 64Mb Flash Memory With FN-NOR Type 4-level Cell", IEEE, Feb. 8, 1996, pp. 36-37.
Mai Son
NEC Corporation
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