Cross-referenced electrostatic discharge protection systems and

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

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361111, 361115, 361118, H02H 900

Patent

active

059993863

ABSTRACT:
An electrostatic discharge protection system provides electrostatic discharge protection for an integrated circuit having a package and a semiconductor device installed within the package. The package includes a first pin, a second pin and a reference pin. The semiconductor device includes a first conductor that connects with the first pin, a second conductor that connects with the second pin, and a reference conductor that connects with the reference pin. The integrated circuit operates within one of a normal operating mode and a power conservation mode when the first and second pins receive a power supply signal. The electrostatic discharge protection system includes a first protection device that detects and couples electrostatic discharge events from the first conductor to the reference conductor by reference to a voltage potential difference between the second conductor and the reference conductor. The electrostatic discharge protection system further includes a second protection device that detects and couples electrostatic discharge events from the second conductor to the reference conductor by reference to a voltage potential difference between the first conductor and the reference conductor. The first and second protection devices are disabled from detecting and coupling electrostatic discharge events when the first and second pins receive the power supply signal regardless of whether the integrated circuit is operating in the normal operating mode or the power conservation mode.

REFERENCES:
patent: 5530612 (1996-06-01), Maloney
patent: 5561577 (1996-10-01), Motley
patent: 5617283 (1997-04-01), Krakauer et al.
Maloney, et al., "Novel Clamp circuits for IC Power Supply Protection," EOS/ESD Symposium 95-1: 1.1.1-1.1.12, Sep. (1995).
Worley, E.R., et al., "Sub-micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions," EOS/ESD Symposium 95-13: 1.2.1-1.2.8, Sep. (1995).
Circuit in PD91-0213, p. 1, (1995).
Cicuit in PCI Bridge, pp. 1-2, (1995).

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