Process for fabricating gate insulating structure of a charge co

Details Process for fabricating gate insulating structure of a charge co Process for fabricating gate insulating structure of a charge co

1992-05-08

1993-08-24

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 42, 437920, 148DIG114, H01L 2176

Patent

active

052388638

ABSTRACT:
A fabrication process includes at least a step of low pressure CVD for depositing an upper silicon oxide layer on a silicon nitride layer which is formed through a lower silicon oxide layer on a silicon substrate, a next step of forming a gate electrode on the second oxide layer, and a further step of selectively removing the second oxide layer and instead forming a similar silicon oxide layer anew. This process can meet the demand for device miniaturization, improve the C-V characteristic of a MOS capacitor and provide uniform insulating layers.

REFERENCES:
patent: 4438157 (1984-03-01), Romano-Moran
patent: 4466172 (1984-08-01), Batra
patent: 4980307 (1990-12-01), Ito et al.
patent: 4987091 (1991-01-01), Kotaki
Chao et al., "Characterization of charge injection and trapping in scaled SONOS/MONOS memory devices", Solid State Electronics, vol. 30, No. 3, pp. 307-319, 1987.

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