Pseudo-random sequence generator arrangement

Details Pseudo-random sequence generator arrangement Pseudo-random sequence generator arrangement

1991-04-09

1992-01-07

Mai, Tan V.

Boots, shoes, and leggings

G06F 102

Patent

active

050797336

ABSTRACT:
The arrangement includes two basic shift registers (1, 3) which are arranged as multipliers whose initial content is predetermined by an internal key, and which are fed back to each other via a modifying member inserted in the loop. The modifying member (5) is an AND-gate controlled by a signal obtained from an OR-gate (8) to whose two inputs the bits which each come from two shift registers (33, 34) which are independent of the two first registers, are applied. These independent registers are modified one by the other, and this modification is effected by inserted bistable counters (10, 11). In addition, the two basic registers (1, 3) are linearly modified by insertion of bits originating from a source (28, 33, 34) which is external to the register to be modified. Each modifier bit is obtained more specifically from an AND-gate (21-25) to whose inputs the bits coming from the two above-mentioned independent registers (33, 34) are conveyed. The output of the pseudo-random sequence is obtained in parallel form by taking off several bits simultaneously from different stages of one of the basic shift registers (1), and the output bits are modified linearly (30, 32), on the basis of bits outputed by the independent registers.

REFERENCES:
patent: 4023026 (1977-05-01), O'Farrell
patent: 4785410 (1988-11-01), Hamatsu et al.
patent: 4845654 (1989-07-01), Harada et al.
patent: 4864525 (1989-09-01), Kurihara et al.

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