Boots – shoes – and leggings
Patent
1989-01-18
1992-01-07
Lall, Parshotam S.
Boots, shoes, and leggings
364489, 364488, G06F 1560
Patent
active
050797174
ABSTRACT:
A method for producing a mask pattern for a semiconductor integrated circuit includes dividing the mask pattern data into a plurality of lower level cells and an upper level cell having wiring lines for providing connections between the lower level cells, extracting inter-cell connection information from the mask pattern data, changing the dimensions of the lower level cells by predetermined ratios to conform to a design standard, and changing the wiring lines of the upper level cell to retain the connection between the lower level cells in accordance with the inter-cell connection information extracted.
REFERENCES:
patent: 4500963 (1985-02-01), Smith et al.
"Compaction Based Custom LSI Layout Design Method", by M. Ishikawa et al., IEEE ICCAD-85, Nov. 18-Nov. 21, 1985, pp. 343-345.
"EXCL: A Circuit Extractor for IC Designs", by S. P. McCormick, IEEE 21st Design Automation Conf., 1984, pp. 616-623.
Nogatch et al., "Automated Design of CMOS Leaf Cells", VLSI Systems Design, Nov. 1985, pp. 66-78.
"Graph-Optimization Techniques for IC Layout and Compaction", Kedem et al.; IEEE Transactions on Computer-Aided Design, vol. CAD-3, No. 1, Jan. 1984.
"Plowing: Interactive Stretching and Compaction in Magic", Scott et al.; Computer Science Division, University of California; 1984.
Lall Parshotam S.
Mitsubishi Denki & Kabushiki Kaisha
Trans V. N.
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