Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Patent
1998-10-27
1999-12-07
Brown, Peter Toby
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
257758, 257760, 257762, 257774, H01L 2710, H01L 2702
Patent
active
059988142
ABSTRACT:
A method of fabricating a semiconductor device having a multi-layered wiring and including dummy wiring not contributing to connection of circuit elements, comprising the steps of: a) preliminarily preparing relationship between width of an isolated lower level wiring and thickness of an interlayer insulating layer with a planarized function formed on the isolated lower level wiring; b) preparing experimental results by forming dense wiring patterns in a first region on a semiconductor substrate, forming an interlayer insulating layer with a planarized function thereon, and measuring thickness of the interlayer insulating layer; c) determining a width of a dummy wiring to be disposed below an isolated upper level wiring, based on the relationship and the measuremental result; d) forming dense lower level wirings in a first region on another semiconductor substrate and a single lower level wiring having the desired width as a dummy wiring only at a location where an upper level wiring is to be formed in a second region on another semiconductor substrate, where an isolated wiring is to be formed as an upper level wiring; e) forming an interlayer insulating layer with a planarizing function to cover the lower level wirings; and f) forming an upper level wirings on the interlayer insulating layer in the first and second regions. A semiconductor device with a multi-layered wiring can be manufactured using a small quantity of data and has upper level wirings on the surfaces of a substantially same level.
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Hirade Seiji
Yamaha Takahisa
Brown Peter Toby
Duong Hung Van
Yamaha Corporation
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