Multiple layer electrode structure for semiconductor device and

Details Multiple layer electrode structure for semiconductor device and Multiple layer electrode structure for semiconductor device and

1989-09-11

1992-01-07

James, Andrew J.

357 67, 357 234, 357 2313, H01L 2348

Patent

active

050796178

ABSTRACT:
A MOS FET comprises a gate electrode and source and drain regions. Conductive layers for electrode are formed on surfaces of the source and drain regions. The conductive layers for electrode are formed by a multilayer structure including a high melting point metal silicide film in contact with the source and drain regions and a polycrystalline silicon layer formed thereon. The gate electrode is formed of polysilicon. The gate electrode has a structure in which part of the gate electrode extends over the conductive layers for electrode formed on the source and drain regions. Such structure reduces the resistance of the interconnection layers for electrodes and realizes reduction in width of the gate electrode. In the manufacturing method, the patterning of the conductive layers for electrodes on the surface of the source/drain regions comprises the steps of etching the polycrystalline silicon layer by dry etching, and etching the high melting point metal silicide layer by wet etching. The wet etching enables etching process without damaging the silicon substrate surface.

REFERENCES:
patent: 4329706 (1982-05-01), Crowder et al.
patent: 4392150 (1983-07-01), Courreges
patent: 4398335 (1983-08-01), Lehrer
patent: 4855798 (1989-08-01), Imamura et al.
patent: 4901134 (1990-02-01), Misawa et al.
M. Y. Tsai et al., "One-Micron Polycide (WSi2 on Poly-Si) MOSFET Technology", Journal of Electrochemical Society, Solid-State Science and Technology (Oct. 1981), presented May 10-16, 1981, pp. 2207-2214.
C. Osburn et al., "High Conductivity Diffusions and Gate Regions Using Self-Aligned Silicide Technology", pp. 212-223.
Huang et al., "A MOS Transistor with Self-Aligned Polysilicon Source-Drain", IEEE Electron Device Letters, vol. EDL-7, No. 5, May 1986, pp. 314-316.
Neues aus der Technik, Nr. 4 vom 15, Aug. 15, 1983 (German).
IBM Technical Disclosure Bulletin, vol. 28 No. 1, Jun. 1985, pp. 26-27.

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