Semiconductor memory device

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357 234, 357 238, 357 6, 357 41, 357 92, H01L 2978, H01L 2702, H01L 4902

Patent

active

050796038

ABSTRACT:
This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.

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patent: 4642881 (1987-02-01), Matsukawa et al.
patent: 4665418 (1987-05-01), Mizutani
patent: 4698787 (1987-10-01), Mukherjee et al.

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