1990-04-30
1992-01-07
James, Andrew J.
357 234, 357 238, 357 6, 357 41, 357 92, H01L 2978, H01L 2702, H01L 4902
Patent
active
050796038
ABSTRACT:
This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.
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Hagiwara Takaaki
Komori Kazuhiro
Kume Hitoshi
Meguro Satoshi
Tsukada Toshihisa
Hitachi , Ltd.
James Andrew J.
Ngo Ngan Van
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