Method for testing an integrated circuit with user definable tra

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G06F 1100

Patent

active

058840230

ABSTRACT:
A method for testing a digital processor 11 in which a test port 1149 is used to transfer trace data from the digital processor to a test host processor 1101 under control of a user definable program which executes in response to predetermined events on the digital processor. Trace data is gathered while an application program loaded in program memory 61 is executed by the digital processor. Trace data is temporarily stored in a trace region 99 of data memory 25 by user definable code which is executed in a background manner by the digital processor in response to trigger events. The trigger events are also enabled by user definable code which enables various portions of analysis hardware 1217. Trace data is transferred from the digital processor to the test host processor through test port 1149 by sending a notification signal to the test host processor by means of message passing register 1216. The digital processor then monitors the message passing register for a handshake signal from the test host processor. When a handshake signal is received, trace data is written into the message passing register by user definable code in a background manner and transferred to the test host processor.

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