Frame checking arrangement for duplex time multiplexed reframing

Details Frame checking arrangement for duplex time multiplexed reframing Frame checking arrangement for duplex time multiplexed reframing

1986-10-30

1988-04-26

Cangialosi, Salvatore

Multiplex communications

Wide area network

Packet switching

370 16, H04J 300, H04J 316

Patent

active

047409614

ABSTRACT:
Telecommunication switching systems are typically connected by high-speed digital data spans. These spans may commonly be T1 or T2 carriers using DS1 or DS2 data formats, respectively. These systems may contain duplex digital span control units. Synchronization circuitry includes a time multiplexed state machine for each copy of the digital span control unit. The state machine monitors framing alarm signals from its own copy as well as from the other copy of the digital span control unit. This circuitry detects whether the framing alarm signals for each copy are identically synchronized. If these framing alarm signals are not identically synchronized, then one copy of the circuitry executes a hold (wait) operation for the other copy of the circuit to perform its reframing operation. For non-error conditions, the wait places the two copies back in synchronization. This arrangement applies stringent checking criteria to framing and synchronization bits, which have been previously found, to insure that these bits are the correct ones. As a result, the duplex units are more likely to remain synchronized.

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