Image processing apparatus and method

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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395109, 358443, 358447, 358448, 358456, 358459, 358465, G06F 1500, H04N 100

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active

058840117

ABSTRACT:
Adders (103, 104) add errors to multi-level image data whose number of bits is reduced by quantization units (101, 102), respectively. Weighted averaging units (120, 121) obtain the weighted average values of binary data of peripheral pixels which have already been divided, respectively. Comparators (107, 108) binarize, on the basis of the weighted average values, the image data output from the adders (103, 104) to obtain binary data corresponding to two pixels obtained upon dividing one pixel of the multi-level data into two pixels. Subtracters (105, 106) obtain the differences between the image data output from the adders (103, 104) and the weighted average values, respectively. Error arithmetic units (109, 110) obtain, on the basis of the differences, errors to be added by the adders (103, 104), respectively. Therefore, when one pixel of multi-level data is divided into two pixels of binary data, a binary image having a high resolution and high gradation can be generated at a low cost.

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patent: 5153925 (1992-10-01), Tanioka et al.
patent: 5315415 (1994-05-01), Kawai et al.
patent: 5394250 (1995-02-01), Shono
patent: 5436736 (1995-07-01), Shono

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