Method for recoverability via redundant cache arrays

Details Method for recoverability via redundant cache arrays Method for recoverability via redundant cache arrays

1997-04-14

1999-03-16

Nguyen, Hoa T.

Excavating

371 103, 39518704, G11C 2900

Patent

active

058839046

ABSTRACT:
A method of correcting an erroneous bit field in a cache used by a processor is disclosed. A first array stores a plurality of bit fields, respectively connected to error checking circuits, and a substitute bit field is supplied for a bit field in the first array that is found to be erroneous by the error checking circuits, the substitute bit field being read from a second array which redundantly stores the bit fields. The error checking circuits can be connected to a parity error control unit which reads the substitute bit field from the second array. The parity error control unit forces the cache into a busy mode when any of the error checking circuits indicates that a bit field is erroneous, and maintains the busy mode until the substitute bit field is supplied. The error checking circuits can check the parity of a plurality of subsets of the bit fields in the first array and indicate which of the subsets are erroneous, and the parity error controller then reads only subsets of the bit fields in the second array corresponding to those subsets in the first array that are erroneous.

REFERENCES:
patent: 4584681 (1986-04-01), Sigh et al.
patent: 4637024 (1987-01-01), Dixon et al.
patent: 5297148 (1994-03-01), Harari et al.
patent: 5590075 (1996-12-01), Mazzali

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