Clock frequency detector for a synchronous memory device

Details Clock frequency detector for a synchronous memory device Clock frequency detector for a synchronous memory device

1997-11-17

1999-03-16

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

326 93, G11C 800

Patent

active

058838538

ABSTRACT:
The present invention employs a clock frequency detector in a SDRAM that detects whether an input clock signal is operating at a fast rate (e.g., 125 MHz or a 8 nanosecond access time), or at a slower rate. In response to the input clock frequency, the clock frequency detector outputs a selection signal to control logic circuitry in the SDRAM indicating whether the SDRAM should operate in either a fast or slow mode. The clock frequency detector employs a frequency detector that detects the frequency of the input clock signal. Based on the frequency of the input clock signal, a selector circuit outputs either a fast or slow selection signal to the control logic circuitry. In response to the fast selection signal, the control logic circuitry performs data access commands at a fast rate, while in response to the slow selection signal, the control logic circuitry executes such commands at a slower, more conservative rate. As a result, the SDRAM device can operate according to its maximum specifications in connection with a fast input clock rate (allowing essentially no margins for error), or perform at a slower rate based on a slower input clock frequency (allowing for some margin of error).

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