Method and circuit for the programming and erasure of a memory

Details Method and circuit for the programming and erasure of a memory Method and circuit for the programming and erasure of a memory

1996-08-27

1999-03-16

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, G11C 1134

Patent

active

058838333

ABSTRACT:
A method and apparatus for the programming and erasure of a memory cell made out of floating-gate transistors and to the circuit pertaining thereto is described. It can be applied especially to non-volatile electrically erasable and programmable memories, for example EEPROMs and flash EPROMs. A programming voltage or erasure voltage including a voltage shift equal in value to a reference voltage is produced, followed by a voltage ramp comprising a rising phase followed possibly by voltage plateau, this voltage ramp being shifted in voltage by the value of the reference voltage and being followed, in turn, by a voltage drop. The value of the voltage shift is fixed at an intermediate value that is lower than the value of a so-called tunnel voltage of the memory cell but greater than the supply voltage.

REFERENCES:
patent: 4996571 (1991-02-01), Kume et al.
patent: 5428568 (1995-06-01), Kobayashi
patent: 5455794 (1995-10-01), Javanifard
patent: 5615153 (1997-03-01), Yiu

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