Reduction of partial product arrays using pre-propagate set-up

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36478604, G06F 752

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active

058838252

ABSTRACT:
There is disclosed a converter for summing inputs includes first, second, third and fourth adders. Each of the adders is adapted to receive a carry-in and to provide as outputs a carry-out and a sum output. Each adder has an associated partial product generated in proximity thereto. The adders are interconnected such that the associated partial product of the first and second adders provide additional inputs to the first adder. The associated partial products of the third and fourth adder provide additional inputs to the second adder. The sum output of the first and second adders provide additional input to the third adder. A sum input to the converter and the sum output of the third adder provide additional inputs to the fourth adder. The output of the fourth adder is the output of the converter.

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"An Architecture for High Speed Array Multiplier" by Islam, et al., IEICE Trans Fundamentals vol. E76 A, No. 8, Aug. 1993, pp. 1326-1333.

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