Modified recessed locos isolation process for deep sub-micron de

Details Modified recessed locos isolation process for deep sub-micron de Modified recessed locos isolation process for deep sub-micron de

1998-03-20

1999-12-07

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438424, 438426, 438435, 438444, 148DIG50, H01L 2176

Patent

active

059982802

ABSTRACT:
A trench is etched in a silicon substrate covered with an oxide
itride stack and a field oxide layer is then grown through oxidation of the silicon in the substrate such that the trench is partly filled. There is reduced oxide encroachment into the active areas under the nitride layer because of the partial field oxide growth. Double oxide layers are deposited over the surface of the field oxide layer and the oxide
itride stack such that the oxide layers fill the remainder of the trench and produce a nearly planar topology. The double oxide layers are then etched back to the nitride layer through chemical mechanical polishing, leaving the field isolation region. After stripping the oxide
itride stack, a gate oxide layer is grown. A minimal amount of oxide is required to fill the trench because the trench is already almost filled with the field oxide layer and because of the shallow depth of the trench. Consequently, the etch back step causes minimal dishing. Further, the field oxide layer rounds the corner between the trench and the active area, obviating the need for a thin oxide liner in the trench.

REFERENCES:
patent: 4842675 (1989-06-01), Chapman et al.
patent: 5498566 (1996-03-01), Lee
patent: 5679602 (1997-10-01), Lin et al.
patent: 5807784 (1998-09-01), Kim
S. Wolf in Silicon Processing for the VLSI Era, vol. 2, pp. 28-31 (Lattice Press, 1990).
S. Wolf in Silicon Processing for the VLSI Era, vol. 2, pp. 45-48 (Lattice Press, 1990).

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