MOS semiconductor device having a low input resistance and a sma

Details MOS semiconductor device having a low input resistance and a sma MOS semiconductor device having a low input resistance and a sma

1987-01-30

1988-04-26

James, Andrew J.

357 68, 357 42, 357 59, 357 2314, H01L 2702

Patent

active

047408251

ABSTRACT:
An opening is formed at a position substantially midway along the widthwise direction of a wide metal wiring layer formed on a semiconductor substrate. A second metal wiring layer is formed in the opening in the same step for forming the wide first metal wiring layer. Drain electrodes of a CMOS inverter formed below the wide first metal wiring layer are connected to the second metal wiring layer through contact holes. The second metal wiring layer is connected to a polycrystalline silicon layer as an output wiring layer through a contact hole.

REFERENCES:
patent: 4152717 (1979-05-01), Satov et al.
patent: 4481524 (1984-11-01), Tsujide
patent: 4541006 (1985-09-01), Ariizumi et al.
Nijhuis et al., "Semiconductor Interface Circuit," IBM Tech. Disclosure Bulletin, vol. 19, No. 10, Mar. 1977.
IBM Technical Disclosure Bulletin, vol. 19, No. 10, pp. 3741-3742, Mar. 1977.

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