Digital phase-locked loop circuit

Details Digital phase-locked loop circuit Digital phase-locked loop circuit

1987-03-09

1987-12-22

Griffin, Robert L.

Pulse or digital communications

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375120, 375 81, 328109, 328155, 307525, 377 43, H03D 324, H04L 704

Patent

active

047150505

ABSTRACT:
During the receipt of a result of comparison from the phase detector representing that the synchronization signal is phase-delayed behind the input signal, the selection circuit sequentially selects the M number of counters, one by one, in a cyclic fashion, in such a direction as to permit the reference clock input to be phase-advanced correspondingly, so that the frequency-divided output signal from the counter to the phase detector can be sequentially phase advanced by 1/M of one cycle of the reference clock. During the receipt of a result of the comparison indicating that the synchronization signal is phase-advanced ahead of the input signal, on the other hand, the selection circuit sequentially selects the M number of counters, one by one, in a cyclic fashion, in such a direction as to allow the reference clock input to be phase-delayed, so that the frequency divided output signal from the counter to the phase detector can be sequentially phase-delayed by 1/M of one cycle of the reference click. When a phase difference occurs between the input signal and the synchronization signal, one cycle time of the synchronization signal is increased or decreased by 1/M of one cycle of the reference clock, thus assuring an enhanced time resolution.

REFERENCES:
patent: 4351000 (1982-09-01), Tokumatsu
patent: 4498103 (1985-02-01), Aschwanden
patent: 4584695 (1986-04-01), Wong et al.

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